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In article <1993Jan21.163607.31684@watson.ibm.com>, pradeep@watson.ibm.com (Pradeep Dubey) writes:
> Are there announced machines (specially micros) with
> some conditional assignment instruction.  I mean
> instruction such as the following:
> 
> MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
> 
> where, c1 refers to some result of some previous compare.


As far as I know the definition of the SPARC architecture
includes conditional moves from version 9 on.
                                ---------

Horst Hogenkamp
.

pradeep@watson.ibm.com (Pradeep Dubey) writes:

>Hello Everyone,
>Are there announced machines (specially micros) with
>some conditional assignment instruction.  I mean
>instruction such as the following:

>MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */

>where, c1 refers to some result of some previous compare.

>Any pointers to such machines or any quantitative evaluation
>of usefulness of this instruction in the specific context
>of some machine would be appreciated.

On the ARM processors all instructions are conditional, so you can
have a MOV<C> R1,R2, which will move R2 to R1 if the condition is
true. To simulate the 3-argument MOVCond you describe, the sequence

	MOV    R1,R3
	MOV<C> R1,R2

or

	MOV<C>  R1,R2
	MOV<~C> R1,R3

can be used. In present ARM implementations these are equally fast.

Digitals Alpha RISC also have conditional moves, as does the proposed
new generation of SPARC. HPs PA-RISC allows some instructions to
conditionally nullify the next instruction. So a 3-argument
conditional move can be implemented with something like

	--- 	  skip if C	\ previous instruction that determines C
	MOV R1,R3 skip always
	MOV R1,R2

with a disclaimer about notation. The idea is that when C is true, the
next instruction is nullified, so MOV R1,R2 is executed. When C is
false, MOV R1,R3 is executed and the MOV R1,R2 nullified.

The designers of these processors obviously felt that it was worth the
effort. It is especially interesting to see that conditional moves are
added to the new SPARC architecture even though they were not part of
the original design. It is difficult to give a good quantitive measure
of the usefulness, but one could try to count the frequency of such
instructions in optimized code.

	Torben Mogensen (torbenm@diku.dk)

Some other machines that have conditional assignment instructions:

1- The IBM TJWatson VLIW, developed by K.Ebcioglu. Its instructions
	are best represented as a tree such as

		if cc1 then
			R1=R2+R3
		else if cc2
`			R2=R3+R4
		else 
		        R3=R4+R5

   In other words, it allows for some form of ANDing of condition codes
to be specified on the (long) instruction.

2- The SIGNETICS LIFE processor: there, every opcode has a third (boolean)
	input. It also is a VLIW

3- The Multiflow TRACE has a "conditional assignment" opcode

	The references are


[1] @Article(IBMVLIW,
        Author="K. Ebcioglu",
        Key="IBM_VLIW",
        Title="Some Design Ideas for a VLIW Architecture for
Sequential-natured Software",
        Journal="Proceeding of the IFIP Working Conference on Parallel
Processing",
        Place="Pisa, Italy",
        Month="April",
        Year="1988")

[2]@Article(LIFE,
        Author="J. Labrousse, G. Slavenburg",
        Key="LIFE",
        Title="CREATE-LIFE: A Design System for High Performance VLSI Circuits",
        Journal="ICCD 1988")

[3]@Article(Colwell88,
        Author="R. P. Colwell et al.",
        Key="Colwell88",
        Title="A VLIW architecture for a trace scheduling compiler",
        Journal="IEEE Trans. Comp.",
        Month="Aug",
        Year="1988")
-- 
	Mauricio Breternitz Jr, Ph.D.	 	mbjr@futserv.austin.ibm.com
	IBM AWD - Internal ZIP 9461
	11400 Burnet Road - Austin, TX 78758
	Austin TX 78758				 phone (512) 838 8531

horst@techfak.uni-bielefeld.de (Horst Hogenkamp) writes:
> As far as I know the definition of the SPARC architecture
> includes conditional moves from version 9 on.

Does anybody know if the SPARC Architecture Manual for version 9 is available
yet? Or any other written documentation for version 9? (I already have the
Architecture Manual for version 8.)

When I asked SPARC International some months ago, I was told that version 9
information was only available to members...

Steinar Haug, system/networks administrator
SINTEF DELAB, University of Trondheim, NORWAY
Email: Steinar.Haug@delab.sintef.no, 
	sthaug@idt.unit.no, steinar@tosca.er.sintef.no

In article <1993Jan21.163607.31684@watson.ibm.com> pradeep@watson.ibm.com  
(Pradeep Dubey) writes:
> Are there announced machines (specially micros) with
> some conditional assignment instruction.  I mean
> instruction such as the following:
> 
> MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
> 
> where, c1 refers to some result of some previous compare.
> 
> Any pointers to such machines or any quantitative evaluation
> of usefulness of this instruction in the specific context
> of some machine would be appreciated.

Unless I'm mistaken, the Multiflow Trace machines had conditional assignment  
instructions. While you certainly wouldn't classify them as micros, they're  
there (or at least were, at one point :-( ). Any ex-Multifloyd's out there  
(DBP? PKR?) might be able to provide more information.

  --Bob

Bob_Beckwith@NeXT.COM
Digital Hardware Engineering
NeXT Computer, Inc.
900 Chesapeake Drive
Redwood City, CA 94063 USA

Pradeep Dubey (pradeep@watson.ibm.com) wrote:
: Hello Everyone,
: Are there announced machines (specially micros) with
: some conditional assignment instruction.  I mean
: instruction such as the following:

: MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */

: where, c1 refers to some result of some previous compare.

: Any pointers to such machines or any quantitative evaluation
: of usefulness of this instruction in the specific context
: of some machine would be appreciated.

: Thanks,
: Pradeep

The above instruction is a 4 operand instruction, as the condition code is
another implicit source operand. The best way to perform a conditional move
is to have compares set or clear all the bits in a register.
Once that is done, conditional moves are simple.

AND R1, R2 -> R4    /* R1 containes the condition code */
ANDNOT R1,R3 -> R4


Gad

In article <1k0840INNjk0@ilx018.intel.com>, gss@ilx018.intel.com (Shavit Amir) writes:
|> The best way to perform a conditional move
|> is to have compares set or clear all the bits in a register.
|> Once that is done, conditional moves are simple.
|> 
|> AND R1, R2 -> R4    /* R1 containes the condition code */
|> ANDNOT R1,R3 -> R4
|> 
|> 
|> Gad

A conditional move is  "if (cond) a = b;"
while your solution is "if (cond) a = b else a = 0"
-- 

...Russ Schnapp
Email: netcom!metaflow!rschnapp or rschnapp@Metaflow.com or rschnapp@BIX.com
Metaflow Technologies   Voice: 619/452-6608x230;  FAX: 619/452-0401
La Jolla, California    Unless otw specified, I`m speaking only for myself!

gss@ilx018.intel.com (Shavit Amir) writes:
] Pradeep Dubey (pradeep@watson.ibm.com) wrote:
] : Hello Everyone,
] : Are there announced machines (specially micros) with
] : some conditional assignment instruction.  I mean
] : instruction such as the following:
]
] : MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
]
] : where, c1 refers to some result of some previous compare.
]
] The above instruction is a 4 operand instruction, as the condition code is
] another implicit source operand. The best way to perform a conditional move
				       ^^^^
] is to have compares set or clear all the bits in a register.
] Once that is done, conditional moves are simple.
]
] AND R1, R2 -> R4    /* R1 containes the condition code */
] ANDNOT R1,R3 -> R4

? Why is
	TEST<cc>, tsrc1, tsrc2, tdst
	AND       tdst, msrc1, mdst
	ANDNOT    tdst, msrc2, mdst

"best" compared to

	TEST        tsrc1, tsrc2
	SELECT<cc>  msrc1, msrc2, mdst

Yes, the first avoids the CC-bits bottleneck, but multiple CCs could do that
without consuming an entire register (a la RS6000). It uses three intructions
instead of two, so it seems a loss to me.

Yes, the latter uses three inputs and one output, where one input
is the CCs. However, add-with-carry does this too, and most architectures
already have it, so it can't be a big deal.
--
Dennis O'Connor			doconnor@sedona.intel.com

In article <6346@rosie.NeXT.COM> Bob_Beckwith@NeXT.COM (Bob Beckwith) writes:
   In article <1993Jan21.163607.31684@watson.ibm.com> pradeep@watson.ibm.com  
   > Are there announced machines (specially micros) with
   > some conditional assignment instruction.  I mean
   > instruction such as the following:
   > 
   > MovCond R1, R2, R3 /* if (c1) R1 <- R2 else R1 <- R3 */
   > 
   > where, c1 refers to some result of some previous compare.
   > 
   > Any pointers to such machines or any quantitative evaluation
   > of usefulness of this instruction in the specific context
   > of some machine would be appreciated.

   Unless I'm mistaken, the Multiflow Trace machines had conditional assignment  
   instructions. While you certainly wouldn't classify them as micros, they're  
   there (or at least were, at one point :-( ). Any ex-Multifloyd's out there  
   (DBP? PKR?) might be able to provide more information.

Hi Bob and Pradeep: Yep, the MFCI Trace VLIWs had conditional moves. Really
handy in certain tight inner loops. To quote from our ASPLOS paper: "We
also included the integer SELECT operation, which provides the semantics of
the C "?" operator without branching." This worked so well that we expanded
this to include other operations in the /500 (which was under construction
when the company croaked) such as conditional stores.

It was a tad messy trying to work SELECTs into the basic ISA, though; this
operator has more sources than normal, so figuring out how to gracefully
specify three sources in an instruction format designed for two is not
trivial. "Graceful", of course, means the compiler code generator guy likes
it.

Bob Colwell  colwell@ichips.intel.com  503-696-4550
Intel Corp.  JF1-19
5200 NE Elam Young Parkway
Hillsboro, Oregon 97124