🚀 go-pugleaf

On Jul 19, 7:04 am, "David L. Jones" <altz...@gmail.com> wrote:
> As promised, an exposé of an issue with the Rigol DS1052E oscilloscope in my
> latest video blog:http://www.alternatezone.com/eevblog/
>
> Dave.
> --
> ---------------------------------------------
> Check out my Electronics Engineering Video Blog & Podcast:http://www.alternatezone.com/eevblog/

You corrected the number of PLLs in the FPGA, how do they get the
clocks' phases aligned? I'm no expert on digital scopes, but I suppose
the clock frequency changes depending on the time base?
Do they just drop some ADCs and keep the frequency, thereby permitting
the use of trace delays to get the 100ps delays or what?
Are the GS/s figures real time or equivalent time?
I think it is possible Rigol tests the ADCs and bins them in-house. Do
you think they might run the power supply a bit "hotter" to get the
parts to work at higher clocks?

"David L. Jones" <altzone@gmail.com> wrote in message 
news:9ZD8m.24080$Qg6.2130@newsfe14.iad...
> As promised, an expos� of an issue with the Rigol DS1052E oscilloscope in 
> my latest video blog:
> http://www.alternatezone.com/eevblog/
>
> Dave.

Does this Rigol claim to do 1Gsps on non periodic signals? If not (like 
other sampling scopes), perhaps they're just sliding the phase of the A-D's 
while still clocking them within their rated specs.

Did you ever measure the clocks to the A-D chips?

Bob
-- 
== All google group posts are automatically deleted due to spam == 

On 19 July, 13:04, "David L. Jones" <altz...@gmail.com> wrote:
> As promised, an exposé of an issue with the Rigol DS1052E oscilloscope in my
> latest video blog:http://www.alternatezone.com/eevblog/
>
> Dave.
> --
> ---------------------------------------------
> Check out my Electronics Engineering Video Blog & Podcast:http://www.alternatezone.com/eevblog/

Obviously their engineers grew up over-clocking AMD/Intel motherboards
then :)

I was initially concerned about the temperature the ad9288-40 is
running at when it's over clocked from 40 to 100Mhz, which won't be an
issue since they have a version that runs at 100Mhz, probably using
the same die.

I'd also be concerned about whether the 40Mhz part can convert at
100Mhz, but looking at the data sheet, there doesn't seem to be any
perceivable difference in the switching/dynamic characteristics, apart
from one each having a specified maximum conversion rate.

As long as the scope perfoms to spec, I don't see anything wrong
otherwise

On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
<altzone@gmail.com> wrote:

>As promised, an expos� of an issue with the Rigol DS1052E oscilloscope in my 
>latest video blog:
>http://www.alternatezone.com/eevblog/
>
>Dave.

Do the scopes work?

John

a7yvm109gf5d1@netzero.com wrote:
> On Jul 19, 7:04 am, "David L. Jones" <altz...@gmail.com> wrote:
>> As promised, an expos� of an issue with the Rigol DS1052E
>> oscilloscope in my
>> latest video blog:http://www.alternatezone.com/eevblog/
>>
>> Dave.
>> --
>> ---------------------------------------------
>> Check out my Electronics Engineering Video Blog &
>> Podcast:http://www.alternatezone.com/eevblog/
>
> You corrected the number of PLLs in the FPGA, how do they get the
> clocks' phases aligned?

Beats me.
Could be as simple as fixed tuned gate delay inside the FPGA, or could be 
some more complex system that auto-calibrates perhaps.

> I'm no expert on digital scopes, but I suppose
> the clock frequency changes depending on the time base?

Only when required when the memory is full.
On short memory mode (1GS/s, 16KB) a relay clicks in at 100ns/div and it 
tells you it's doing 1GS/s on 50ns/div to 5ns/div.
No such click occurs when in long memory mode (500MS/s 1Mpoints), and it 
stays on 500MS/s up to 100ns/div.
The relay is thus most likley switching the input signal between either 5 or 
10 ADC's depending upon the requirement.

> Do they just drop some ADCs and keep the frequency, thereby permitting
> the use of trace delays to get the 100ps delays or what?
> Are the GS/s figures real time or equivalent time?

1GS/s real time of course, that's been the selling point of these Rigol 
scopes for the last 5 years or so.

> I think it is possible Rigol tests the ADCs and bins them in-house. Do
> you think they might run the power supply a bit "hotter" to get the
> parts to work at higher clocks?

I don't think so, likely they have just done exhaustive testing of these 
parts to ensure the work. Binning each one in house would be possible, but 
messy.
Perhaps AD are the ones pulling the swifty and charging a huge premium 
(almost 3 times) for the exact same part?

Dave.
-- 
---------------------------------------------
Check out my Electronics Engineering Video Blog & Podcast:
http://www.alternatezone.com/eevblog/ 

BobW wrote:
> "David L. Jones" <altzone@gmail.com> wrote in message
> news:9ZD8m.24080$Qg6.2130@newsfe14.iad...
>> As promised, an expos� of an issue with the Rigol DS1052E
>> oscilloscope in my latest video blog:
>> http://www.alternatezone.com/eevblog/
>>
>> Dave.
>
> Does this Rigol claim to do 1Gsps on non periodic signals?

Yes, that's always been its big selling point. 1GS/s real-time.

> If not
> (like other sampling scopes), perhaps they're just sliding the phase
> of the A-D's while still clocking them within their rated specs.

It also has a selectable equivalent time sampling mode (up to 10GS/s), but 
you have to specifically select this through a menu.
In this mode the 1Mpoint memory comes in at 100ns/div.

> Did you ever measure the clocks to the A-D chips?

No, I haven't open my unit. But bet your bottom dollar they are 100MHz, 
simply no other way to do it.

Dave.

-- 
---------------------------------------------
Check out my Electronics Engineering Video Blog & Podcast:
http://www.alternatezone.com/eevblog/ 

John Larkin wrote:
> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
> <altzone@gmail.com> wrote:
>
>> As promised, an expos� of an issue with the Rigol DS1052E
>> oscilloscope in my latest video blog:
>> http://www.alternatezone.com/eevblog/
>>
>> Dave.
>
> Do the scopes work?

Yep, they work. So Rigol are obviously getting away with it by hook or by 
crook.
If AD are deliberately under-speccing their normal chips, then it's a clever 
ploy by Rigol to exploit it.

Dave.
-- 
---------------------------------------------
Check out my Electronics Engineering Video Blog & Podcast:
http://www.alternatezone.com/eevblog/ 

"David L. Jones" <altzone@gmail.com> wrote in message 
news:aAM8m.14055$8B7.9612@newsfe20.iad...
> a7yvm109gf5d1@netzero.com wrote:
>> On Jul 19, 7:04 am, "David L. Jones" <altz...@gmail.com> wrote:
>>> As promised, an expos� of an issue with the Rigol DS1052E
>>> oscilloscope in my
>>> latest video blog:http://www.alternatezone.com/eevblog/
>>>
>>> Dave.
>>> --
>>> ---------------------------------------------
>>> Check out my Electronics Engineering Video Blog &
>>> Podcast:http://www.alternatezone.com/eevblog/
>>
>> You corrected the number of PLLs in the FPGA, how do they get the
>> clocks' phases aligned?
>
> Beats me.
> Could be as simple as fixed tuned gate delay inside the FPGA, or could 
> be some more complex system that auto-calibrates perhaps.
>
>> I'm no expert on digital scopes, but I suppose
>> the clock frequency changes depending on the time base?
>
> Only when required when the memory is full.
> On short memory mode (1GS/s, 16KB) a relay clicks in at 100ns/div and 
> it tells you it's doing 1GS/s on 50ns/div to 5ns/div.
> No such click occurs when in long memory mode (500MS/s 1Mpoints), and 
> it stays on 500MS/s up to 100ns/div.
> The relay is thus most likley switching the input signal between 
> either 5 or 10 ADC's depending upon the requirement.
>
>> Do they just drop some ADCs and keep the frequency, thereby 
>> permitting
>> the use of trace delays to get the 100ps delays or what?
>> Are the GS/s figures real time or equivalent time?
>
> 1GS/s real time of course, that's been the selling point of these 
> Rigol scopes for the last 5 years or so.
>
>> I think it is possible Rigol tests the ADCs and bins them in-house. 
>> Do
>> you think they might run the power supply a bit "hotter" to get the
>> parts to work at higher clocks?
>
> I don't think so, likely they have just done exhaustive testing of 
> these parts to ensure the work. Binning each one in house would be 
> possible, but messy.
> Perhaps AD are the ones pulling the swifty and charging a huge premium 
> (almost 3 times) for the exact same part?
>
> Dave.
> -- 

It could have been a purchasing error, that actually works.
Or, the parts marked as 40 don�t meet the specs over temperature for a 
100/80 mhz clock.
Perhaps  NL specs are not met but Rigol can compensate for the error.
I've seen -40c to 85c parts work beyond the rated specs, with some 
additional error.

Cheers
 

PS: Another piece of consumer electronics that was on the shelves for
10 years was the Commodore 64. I'm sure it underwent internal changes
but it was the same machine for years.

On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
<altzone@gmail.com> wrote:

>a7yvm109gf5d1@netzero.com wrote:

<snip>

>> You corrected the number of PLLs in the FPGA, how do they get the
>> clocks' phases aligned?
>
>Beats me.
>Could be as simple as fixed tuned gate delay inside the FPGA, or could be 
>some more complex system that auto-calibrates perhaps.

Tuning gate delays in an FPGA doesn't work.  Routing is over half the
delay and there is no way to fix that part.  Every time you "wire" the
part it'll have a different routing and your delays will be off.
Indeed, the idea is to make sure you don't rely on placement or
routing.

<snip>

On 19 July, 23:02, "David L. Jones" <altz...@gmail.com> wrote:
> John Larkin wrote:
> > On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
> > <altz...@gmail.com> wrote:
>
> >> As promised, an exposé of an issue with the Rigol DS1052E
> >> oscilloscope in my latest video blog:
> >>http://www.alternatezone.com/eevblog/
>
> >> Dave.
>
> > Do the scopes work?
>
> Yep, they work. So Rigol are obviously getting away with it by hook or by
> crook.
> If AD are deliberately under-speccing their normal chips, then it's a clever
> ploy by Rigol to exploit it.
>
> Dave.
> --
> ---------------------------------------------
> Check out my Electronics Engineering Video Blog & Podcast:http://www.alternatezone.com/eevblog/

So give it a 1 Ghz signal and see if it it looks right then.

On Jul 19, 4:52 pm, "David L. Jones" <altz...@gmail.com> wrote:
>
> I don't think so, likely they have just done exhaustive testing of these
> parts to ensure the work. Binning each one in house would be possible, but
> messy.
> Perhaps AD are the ones pulling the swifty and charging a huge premium
> (almost 3 times) for the exact same part?

Why not? I'm pretty sure a 50MHz and 100MHz are exactly the same
too.... :)

On Jul 19, 9:09 pm, a7yvm109gf...@netzero.com wrote:
> On Jul 19, 4:52 pm, "David L. Jones" <altz...@gmail.com> wrote:
>
>
>
> > I don't think so, likely they have just done exhaustive testing of these
> > parts to ensure the work. Binning each one in house would be possible, but
> > messy.
> > Perhaps AD are the ones pulling the swifty and charging a huge premium
> > (almost 3 times) for the exact same part?
>
> Why not? I'm pretty sure a 50MHz and 100MHz are exactly the same
> too.... :)

I meant a 50MHz and 100MHz scope up there.

a7yvm109gf5d1@netzero.com wrote:
> On Jul 19, 9:09 pm, a7yvm109gf...@netzero.com wrote:
>> On Jul 19, 4:52 pm, "David L. Jones" <altz...@gmail.com> wrote:
>>
>>
>>
>>> I don't think so, likely they have just done exhaustive testing of
>>> these parts to ensure the work. Binning each one in house would be
>>> possible, but messy.
>>> Perhaps AD are the ones pulling the swifty and charging a huge
>>> premium (almost 3 times) for the exact same part?
>>
>> Why not? I'm pretty sure a 50MHz and 100MHz are exactly the same
>> too.... :)
>
> I meant a 50MHz and 100MHz scope up there.

Maybe, and I've mentioned this in a previous blog comment.
There is a chance the 50MHz and 100MHz model front ends are identical except 
for maybe some different value parts on the 50MHz model to limit the 
bandwidth.
Would be interesting to see both circuits side-by-side.
Given that both sample at 1GS/s and everything else is indentical too, 
modding the 50MHz unit might just be possible.

Dave.

-- 
================================================
Check out my Electronics Engineering Video Blog & Podcast:
http://www.alternatezone.com/eevblog/

blackhead <larryharson@softhome.net> wrote in
news:0268880f-5658-44fe-8908-579f2f1031ba@s31g2000yqs.googlegroups.com: 

> On 19 July, 23:02, "David L. Jones" <altz...@gmail.com> wrote:
>> John Larkin wrote:
>>
>> > Do the scopes work?
>>
>> Yep, they work. So Rigol are obviously getting away with it by hook
>> or by crook.
>> If AD are deliberately under-speccing their normal chips, then it's a
>> clever ploy by Rigol to exploit it.
>>
>> Dave.
>> --
>> ---------------------------------------------
>> Check out my Electronics Engineering Video Blog &
>> Podcast:http://www.alternatezone.com/eevblog/
> 
> So give it a 1 Ghz signal and see if it it looks right then.
> 

Umm, no. Ever heard of Nyquist?

Plus to see anything like a signal for your eye's benefit, you're better 
off with x10 sampling. 

So 100MHz is more on the mark. Does it allow you to simply plot the points 
without the "join the dots"?

BTW if you had exactly 1GHz going in, and it manged to sneak pass the front 
end, you'd end up with a straight line at some DC level.

Ray

Ray wrote:
> blackhead <larryharson@softhome.net> wrote in
> news:0268880f-5658-44fe-8908-579f2f1031ba@s31g2000yqs.googlegroups.com:
>
>> On 19 July, 23:02, "David L. Jones" <altz...@gmail.com> wrote:
>>> John Larkin wrote:
>>>
>>>> Do the scopes work?
>>>
>>> Yep, they work. So Rigol are obviously getting away with it by hook
>>> or by crook.
>>> If AD are deliberately under-speccing their normal chips, then it's
>>> a clever ploy by Rigol to exploit it.
>>>
>>> Dave.
>>> --
>>> ---------------------------------------------
>>> Check out my Electronics Engineering Video Blog &
>>> Podcast:http://www.alternatezone.com/eevblog/
>>
>> So give it a 1 Ghz signal and see if it it looks right then.
>>
>
> Umm, no. Ever heard of Nyquist?
>
> Plus to see anything like a signal for your eye's benefit, you're
> better off with x10 sampling.
>
> So 100MHz is more on the mark. Does it allow you to simply plot the
> points without the "join the dots"?

Yep. You can choose between dots, linear ("join the dots") vector 
intepolation, or sinX/x interpolation.

> BTW if you had exactly 1GHz going in, and it manged to sneak pass the
> front end

That would be a neat trick!

Dave.

-- 
---------------------------------------------
Check out my Electronics Engineering Video Blog & Podcast:
http://www.alternatezone.com/eevblog/ 

On 20 July, 10:06, Ray <s...@spamalot.com> wrote:
> blackhead <larryhar...@softhome.net> wrote innews:0268880f-5658-44fe-8908-579f2f1031ba@s31g2000yqs.googlegroups.com:
>
>
>
>
>
> > On 19 July, 23:02, "David L. Jones" <altz...@gmail.com> wrote:
> >> John Larkin wrote:
>
> >> > Do the scopes work?
>
> >> Yep, they work. So Rigol are obviously getting away with it by hook
> >> or by crook.
> >> If AD are deliberately under-speccing their normal chips, then it's a
> >> clever ploy by Rigol to exploit it.
>
> >> Dave.
> >> --
> >> ---------------------------------------------
> >> Check out my Electronics Engineering Video Blog &
> >> Podcast:http://www.alternatezone.com/eevblog/
>
> > So give it a 1 Ghz signal and see if it it looks right then.
>
> Umm, no. Ever heard of Nyquist?
>
> Plus to see anything like a signal for your eye's benefit, you're better
> off with x10 sampling.
>
> So 100MHz is more on the mark. Does it allow you to simply plot the points
> without the "join the dots"?
>
> BTW if you had exactly 1GHz going in, and it manged to sneak pass the front
> end, you'd end up with a straight line at some DC level.
>
> Ray- Hide quoted text -
>
> - Show quoted text -

I have heard of Nyquist, just forgot to apply him in this case :)
There will be an anti aliasing filter in the front end so you wont see
much if you put in anything close to half the sampling rate = 500Mhz.
Or maybe Rigol has decided to cut corners and got rid of it
completely ;)

blackhead wrote:
> On 20 July, 10:06, Ray <s...@spamalot.com> wrote:
>> blackhead <larryhar...@softhome.net> wrote
>> innews:0268880f-5658-44fe-8908-579f2f1031ba@s31g2000yqs.googlegroups.com:
>>
>>
>>
>>
>>
>>> On 19 July, 23:02, "David L. Jones" <altz...@gmail.com> wrote:
>>>> John Larkin wrote:
>>
>>>>> Do the scopes work?
>>
>>>> Yep, they work. So Rigol are obviously getting away with it by hook
>>>> or by crook.
>>>> If AD are deliberately under-speccing their normal chips, then
>>>> it's a clever ploy by Rigol to exploit it.
>>
>>>> Dave.
>>>> --
>>>> ---------------------------------------------
>>>> Check out my Electronics Engineering Video Blog &
>>>> Podcast:http://www.alternatezone.com/eevblog/
>>
>>> So give it a 1 Ghz signal and see if it it looks right then.
>>
>> Umm, no. Ever heard of Nyquist?
>>
>> Plus to see anything like a signal for your eye's benefit, you're
>> better
>> off with x10 sampling.
>>
>> So 100MHz is more on the mark. Does it allow you to simply plot the
>> points
>> without the "join the dots"?
>>
>> BTW if you had exactly 1GHz going in, and it manged to sneak pass
>> the front
>> end, you'd end up with a straight line at some DC level.
>>
>> Ray- Hide quoted text -
>>
>> - Show quoted text -
>
> I have heard of Nyquist, just forgot to apply him in this case :)

and you forgot about the analog bandwidth too, that's kinda important!

> There will be an anti aliasing filter in the front end so you wont see
> much if you put in anything close to half the sampling rate = 500Mhz.

Err, the front end bandwidth is only 50MHz!
Kinda hard for any signals higher than that to sneak past, as Ray said.

Dave.

-- 
---------------------------------------------
Check out my Electronics Engineering Video Blog & Podcast:
http://www.alternatezone.com/eevblog/ 

On Mon, 20 Jul 2009 08:02:20 +1000, "David L. Jones"
<altzone@gmail.com> wrote:

>John Larkin wrote:
>> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
>> <altzone@gmail.com> wrote:
>>
>>> As promised, an expos� of an issue with the Rigol DS1052E
>>> oscilloscope in my latest video blog:
>>> http://www.alternatezone.com/eevblog/
>>>
>>> Dave.
>>
>> Do the scopes work?
>
>Yep, they work. So Rigol are obviously getting away with it by hook or by 
>crook.
>If AD are deliberately under-speccing their normal chips, then it's a clever 
>ploy by Rigol to exploit it.
>
>Dave.

We overclock/overstress parts when there's a substantial payoff. One
Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so
we run it at 20. One microwave schottky diode is rated for 2 volts
reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an
FPGA can buy some timing margin. Some diodes and cmos parts leak four
or five orders of magnitide less than the datasheet guarantees. An
0603 resistor can dissipate a quarter of a watt safely. The trick is
to take calibrated risks where there's demonstrated margin and big
paybacks, and take zero risk everywhere else.

John

John Larkin wrote:
> On Mon, 20 Jul 2009 08:02:20 +1000, "David L. Jones"
> <altzone@gmail.com> wrote:
> 
>> John Larkin wrote:
>>> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
>>> <altzone@gmail.com> wrote:
>>>
>>>> As promised, an expos� of an issue with the Rigol DS1052E
>>>> oscilloscope in my latest video blog:
>>>> http://www.alternatezone.com/eevblog/
>>>>
>>>> Dave.
>>> Do the scopes work?
>> Yep, they work. So Rigol are obviously getting away with it by hook or by 
>> crook.
>> If AD are deliberately under-speccing their normal chips, then it's a clever 
>> ploy by Rigol to exploit it.
>>
>> Dave.
> 
> We overclock/overstress parts when there's a substantial payoff. One
> Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so
> we run it at 20. One microwave schottky diode is rated for 2 volts
> reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an
> FPGA can buy some timing margin. Some diodes and cmos parts leak four
> or five orders of magnitide less than the datasheet guarantees. An
> 0603 resistor can dissipate a quarter of a watt safely. The trick is
> to take calibrated risks where there's demonstrated margin and big
> paybacks, and take zero risk everywhere else.
> 
> John
> 

Doesn't the manufacturer sort of put themselves at risk that the chip 
vendor decides to change the process or ship marginal product ("Nobody 
is buying our 100 MHz parts anymore, so we will save a few bucks and 
make and ship 40 MHz parts (that pass only to 45 MHz)")?

-- 
Joe Leikhim K4SAT
"The RFI-EMI-GUY"�

"Use only Genuine Interocitor Parts" Tom Servo  ;-P

"RFI-EMI-GUY" <Rhyolite@NETTALLY.COM> wrote in message 
news:4a64ac0d$0$5646$9a6e19ea@unlimited.newshosting.com...
> John Larkin wrote:
>> On Mon, 20 Jul 2009 08:02:20 +1000, "David L. Jones"
>> <altzone@gmail.com> wrote:
>>
>>> John Larkin wrote:
>>>> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
>>>> <altzone@gmail.com> wrote:
>>>>
>>>>> As promised, an expos� of an issue with the Rigol DS1052E
>>>>> oscilloscope in my latest video blog:
>>>>> http://www.alternatezone.com/eevblog/
>>>>>
>>>>> Dave.
>>>> Do the scopes work?
>>> Yep, they work. So Rigol are obviously getting away with it by hook or 
>>> by crook.
>>> If AD are deliberately under-speccing their normal chips, then it's a 
>>> clever ploy by Rigol to exploit it.
>>>
>>> Dave.
>>
>> We overclock/overstress parts when there's a substantial payoff. One
>> Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so
>> we run it at 20. One microwave schottky diode is rated for 2 volts
>> reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an
>> FPGA can buy some timing margin. Some diodes and cmos parts leak four
>> or five orders of magnitide less than the datasheet guarantees. An
>> 0603 resistor can dissipate a quarter of a watt safely. The trick is
>> to take calibrated risks where there's demonstrated margin and big
>> paybacks, and take zero risk everywhere else.
>>
>> John
>>
>
> Doesn't the manufacturer sort of put themselves at risk that the chip 
> vendor decides to change the process or ship marginal product ("Nobody is 
> buying our 100 MHz parts anymore, so we will save a few bucks and make and 
> ship 40 MHz parts (that pass only to 45 MHz)")?
>
> -- 
> Joe Leikhim K4SAT

Yep. That's what I would be extremely concerned about. If I ever decided to 
run a part over its rated limits (speed wise), I would put in hooks, for 
production testing, to lower its supplies to their minimum and then run 
those tests at the maximum rated d.u.t. temperature.

Of course, in Larkin's case, the only person that can fire him for non 
performance and insubordination is his wife.

Bob
-- 
== All google group posts are automatically deleted due to spam == 

On 20 July, 12:54, "David L. Jones" <altz...@gmail.com> wrote:
> blackhead wrote:
> > On 20 July, 10:06, Ray <s...@spamalot.com> wrote:
> >> blackhead <larryhar...@softhome.net> wrote
> >> innews:0268880f-5658-44fe-8908-579f2f1031ba@s31g2000yqs.googlegroups.com:
>
> >>> On 19 July, 23:02, "David L. Jones" <altz...@gmail.com> wrote:
> >>>> John Larkin wrote:
>
> >>>>> Do the scopes work?
>
> >>>> Yep, they work. So Rigol are obviously getting away with it by hook
> >>>> or by crook.
> >>>> If AD are deliberately under-speccing their normal chips, then
> >>>> it's a clever ploy by Rigol to exploit it.
>
> >>>> Dave.
> >>>> --
> >>>> ---------------------------------------------
> >>>> Check out my Electronics Engineering Video Blog &
> >>>> Podcast:http://www.alternatezone.com/eevblog/
>
> >>> So give it a 1 Ghz signal and see if it it looks right then.
>
> >> Umm, no. Ever heard of Nyquist?
>
> >> Plus to see anything like a signal for your eye's benefit, you're
> >> better
> >> off with x10 sampling.
>
> >> So 100MHz is more on the mark. Does it allow you to simply plot the
> >> points
> >> without the "join the dots"?
>
> >> BTW if you had exactly 1GHz going in, and it manged to sneak pass
> >> the front
> >> end, you'd end up with a straight line at some DC level.
>
> >> Ray- Hide quoted text -
>
> >> - Show quoted text -
>
> > I have heard of Nyquist, just forgot to apply him in this case :)
>
> and you forgot about the analog bandwidth too, that's kinda important!
>
> > There will be an anti aliasing filter in the front end so you wont see
> > much if you put in anything close to half the sampling rate = 500Mhz.
>
> Err, the front end bandwidth is only 50MHz!
> Kinda hard for any signals higher than that to sneak past, as Ray said.

Yes, but that's the 3dB bandwidth, isn't it? i.e the frequency at
which the voltage is 1/sqrt2 that of its value at DC. Hence you should
still be able to see signals higher than 50Mhz. Plonk a signal
generator on it and tell us what you you see ;)


> Dave.
>
> --
> ---------------------------------------------
> Check out my Electronics Engineering Video Blog & Podcast:http://www.alternatezone.com/eevblog/- Hide quoted text -
>
> - Show quoted text -

On Mon, 20 Jul 2009 11:00:40 -0700, "BobW"
<nimby_GIMME_SOME_SPAM@roadrunner.com> wrote:

>
>"RFI-EMI-GUY" <Rhyolite@NETTALLY.COM> wrote in message 
>news:4a64ac0d$0$5646$9a6e19ea@unlimited.newshosting.com...
>> John Larkin wrote:
>>> On Mon, 20 Jul 2009 08:02:20 +1000, "David L. Jones"
>>> <altzone@gmail.com> wrote:
>>>
>>>> John Larkin wrote:
>>>>> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
>>>>> <altzone@gmail.com> wrote:
>>>>>
>>>>>> As promised, an expos� of an issue with the Rigol DS1052E
>>>>>> oscilloscope in my latest video blog:
>>>>>> http://www.alternatezone.com/eevblog/
>>>>>>
>>>>>> Dave.
>>>>> Do the scopes work?
>>>> Yep, they work. So Rigol are obviously getting away with it by hook or 
>>>> by crook.
>>>> If AD are deliberately under-speccing their normal chips, then it's a 
>>>> clever ploy by Rigol to exploit it.
>>>>
>>>> Dave.
>>>
>>> We overclock/overstress parts when there's a substantial payoff. One
>>> Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so
>>> we run it at 20. One microwave schottky diode is rated for 2 volts
>>> reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an
>>> FPGA can buy some timing margin. Some diodes and cmos parts leak four
>>> or five orders of magnitide less than the datasheet guarantees. An
>>> 0603 resistor can dissipate a quarter of a watt safely. The trick is
>>> to take calibrated risks where there's demonstrated margin and big
>>> paybacks, and take zero risk everywhere else.
>>>
>>> John
>>>
>>
>> Doesn't the manufacturer sort of put themselves at risk that the chip 
>> vendor decides to change the process or ship marginal product ("Nobody is 
>> buying our 100 MHz parts anymore, so we will save a few bucks and make and 
>> ship 40 MHz parts (that pass only to 45 MHz)")?
>>
>> -- 
>> Joe Leikhim K4SAT
>
>Yep. That's what I would be extremely concerned about. If I ever decided to 
>run a part over its rated limits (speed wise), I would put in hooks, for 
>production testing, to lower its supplies to their minimum and then run 
>those tests at the maximum rated d.u.t. temperature.
>
>Of course, in Larkin's case, the only person that can fire him for non 
>performance and insubordination is his wife.
>

Hey, nowadays I report to The Brat.

John

On Mon, 20 Jul 2009 13:40:41 -0400, RFI-EMI-GUY
<Rhyolite@NETTALLY.COM> wrote:

>John Larkin wrote:
>> On Mon, 20 Jul 2009 08:02:20 +1000, "David L. Jones"
>> <altzone@gmail.com> wrote:
>> 
>>> John Larkin wrote:
>>>> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
>>>> <altzone@gmail.com> wrote:
>>>>
>>>>> As promised, an expos� of an issue with the Rigol DS1052E
>>>>> oscilloscope in my latest video blog:
>>>>> http://www.alternatezone.com/eevblog/
>>>>>
>>>>> Dave.
>>>> Do the scopes work?
>>> Yep, they work. So Rigol are obviously getting away with it by hook or by 
>>> crook.
>>> If AD are deliberately under-speccing their normal chips, then it's a clever 
>>> ploy by Rigol to exploit it.
>>>
>>> Dave.
>> 
>> We overclock/overstress parts when there's a substantial payoff. One
>> Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so
>> we run it at 20. One microwave schottky diode is rated for 2 volts
>> reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an
>> FPGA can buy some timing margin. Some diodes and cmos parts leak four
>> or five orders of magnitide less than the datasheet guarantees. An
>> 0603 resistor can dissipate a quarter of a watt safely. The trick is
>> to take calibrated risks where there's demonstrated margin and big
>> paybacks, and take zero risk everywhere else.
>> 
>> John
>> 
>
>Doesn't the manufacturer sort of put themselves at risk that the chip 
>vendor decides to change the process or ship marginal product ("Nobody 
>is buying our 100 MHz parts anymore, so we will save a few bucks and 
>make and ship 40 MHz parts (that pass only to 45 MHz)")?

Sure. Life is risky. Given a product with 200 different parts, two of
which are overstressed, there's probably more risk that one of the 198
other parts will be EOL'd.

John

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
> Sure. Life is risky. Given a product with 200 different parts, two of
> which are overstressed, there's probably more risk that one of the 198
> other parts will be EOL'd.

Have you ever been caught in the situation of one of your over-stressed parts 
being changed by the manufacturer in such a way so as to render it unsuitable 
for your needs?

John Larkin wrote:
> On Mon, 20 Jul 2009 11:00:40 -0700, "BobW"
> <nimby_GIMME_SOME_SPAM@roadrunner.com> wrote:
> 
>> "RFI-EMI-GUY" <Rhyolite@NETTALLY.COM> wrote in message 
>> news:4a64ac0d$0$5646$9a6e19ea@unlimited.newshosting.com...
>>> John Larkin wrote:
>>>> On Mon, 20 Jul 2009 08:02:20 +1000, "David L. Jones"
>>>> <altzone@gmail.com> wrote:
>>>>
>>>>> John Larkin wrote:
>>>>>> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
>>>>>> <altzone@gmail.com> wrote:
>>>>>>
>>>>>>> As promised, an expos� of an issue with the Rigol DS1052E
>>>>>>> oscilloscope in my latest video blog:
>>>>>>> http://www.alternatezone.com/eevblog/
>>>>>>>
>>>>>>> Dave.
>>>>>> Do the scopes work?
>>>>> Yep, they work. So Rigol are obviously getting away with it by hook or 
>>>>> by crook.
>>>>> If AD are deliberately under-speccing their normal chips, then it's a 
>>>>> clever ploy by Rigol to exploit it.
>>>>>
>>>>> Dave.
>>>> We overclock/overstress parts when there's a substantial payoff. One
>>>> Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so
>>>> we run it at 20. One microwave schottky diode is rated for 2 volts
>>>> reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an
>>>> FPGA can buy some timing margin. Some diodes and cmos parts leak four
>>>> or five orders of magnitide less than the datasheet guarantees. An
>>>> 0603 resistor can dissipate a quarter of a watt safely. The trick is
>>>> to take calibrated risks where there's demonstrated margin and big
>>>> paybacks, and take zero risk everywhere else.
>>>>
>>>> John
>>>>
>>> Doesn't the manufacturer sort of put themselves at risk that the chip 
>>> vendor decides to change the process or ship marginal product ("Nobody is 
>>> buying our 100 MHz parts anymore, so we will save a few bucks and make and 
>>> ship 40 MHz parts (that pass only to 45 MHz)")?
>>>
>>> -- 
>>> Joe Leikhim K4SAT
>> Yep. That's what I would be extremely concerned about. If I ever decided to 
>> run a part over its rated limits (speed wise), I would put in hooks, for 
>> production testing, to lower its supplies to their minimum and then run 
>> those tests at the maximum rated d.u.t. temperature.
>>
>> Of course, in Larkin's case, the only person that can fire him for non 
>> performance and insubordination is his wife.
>>
> 
> Hey, nowadays I report to The Brat.
> 

I was just going to say, didn't she show an interest in the biz lately 
and even do a layout? Remember, she may one day be the one deciding 
which nursing home you guys go to ;-)

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

Joel Koltner wrote:
> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
>> Sure. Life is risky. Given a product with 200 different parts, two of
>> which are overstressed, there's probably more risk that one of the 198
>> other parts will be EOL'd.
> 
> Have you ever been caught in the situation of one of your over-stressed parts 
> being changed by the manufacturer in such a way so as to render it unsuitable 
> for your needs?
> 

Happened to another engineer: Bought tons of 5% capacitors for 
production, went into Hilbert shifters. They always hand-picked the 1% 
parts out of this lot and used the rest for jelly-bean stuffing. One 
balmy summer day they found the first shipment that had a hole smack in 
the middle of the Gaussian tolerance curve. Obviously someone had 
detected a business opprotunity ... whoops.

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

Joel Koltner wrote:
> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in
> message
>> Sure. Life is risky. Given a product with 200 different parts, two of
>> which are overstressed, there's probably more risk that one of the
>> 198 other parts will be EOL'd.
>
> Have you ever been caught in the situation of one of your
> over-stressed parts being changed by the manufacturer in such a way
> so as to render it unsuitable for your needs?

I've never been caught with any over-spec parts I've used in the past. It's 
always something else in the design that goes the way of the do-do. And of 
course it's always the seemingly most innocuous part.

Dave.
-- 
---------------------------------------------
Check out my Electronics Engineering Video Blog & Podcast:
http://www.alternatezone.com/eevblog/ 

Joerg wrote:
> Joel Koltner wrote:
>> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>> message
>>> Sure. Life is risky. Given a product with 200 different parts, two of
>>> which are overstressed, there's probably more risk that one of the 198
>>> other parts will be EOL'd.
>>
>> Have you ever been caught in the situation of one of your 
>> over-stressed parts being changed by the manufacturer in such a way so 
>> as to render it unsuitable for your needs?
>>
> 
> Happened to another engineer: Bought tons of 5% capacitors for 
> production, went into Hilbert shifters. They always hand-picked the 1% 
> parts out of this lot and used the rest for jelly-bean stuffing. One 
> balmy summer day they found the first shipment that had a hole smack in 
> the middle of the Gaussian tolerance curve. Obviously someone had 
> detected a business opprotunity ... whoops.
> 

Sure production ends on the part and then they look in the stockroom and 
find a dusty box of parts, where did they come from? Probably someone 
else hand picked parts and sent the rest back for restock!

-- 
Joe Leikhim K4SAT
"The RFI-EMI-GUY"�

"Use only Genuine Interocitor Parts" Tom Servo  ;-P

RFI-EMI-GUY wrote:
> Joerg wrote:
>> Joel Koltner wrote:
>>> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>>> message
>>>> Sure. Life is risky. Given a product with 200 different parts, two of
>>>> which are overstressed, there's probably more risk that one of the 198
>>>> other parts will be EOL'd.
>>>
>>> Have you ever been caught in the situation of one of your 
>>> over-stressed parts being changed by the manufacturer in such a way 
>>> so as to render it unsuitable for your needs?
>>>
>>
>> Happened to another engineer: Bought tons of 5% capacitors for 
>> production, went into Hilbert shifters. They always hand-picked the 1% 
>> parts out of this lot and used the rest for jelly-bean stuffing. One 
>> balmy summer day they found the first shipment that had a hole smack 
>> in the middle of the Gaussian tolerance curve. Obviously someone had 
>> detected a business opprotunity ... whoops.
>>
> 
> Sure production ends on the part and then they look in the stockroom and 
> find a dusty box of parts, where did they come from? Probably someone 
> else hand picked parts and sent the rest back for restock!
> 

They couldn't be that brazen unless they'd have gone to great lengths 
such as re-belting them all. Because the good ones weren't all in front 
section.

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

blackhead <larryharson@softhome.net> wrote in
news:f68bfd0f-8827-4cb3-8b05-c9e0ddec8ec4@a7g2000yqk.googlegroups.com: 

> On 20 July, 10:06, Ray <s...@spamalot.com> wrote:
>> blackhead <larryhar...@softhome.net> wrote
>> innews:0268880f-5658-44fe-8908-
579f2f1031ba@s31g2000yqs.googlegroups.c
>> om: 
>>
>>
>> > So give it a 1 Ghz signal and see if it it looks right then.
>>
>> Umm, no. Ever heard of Nyquist?
>>
>>
>> BTW if you had exactly 1GHz going in, and it manged to sneak pass the
>> front end, you'd end up with a straight line at some DC level.
>>
>> Ray
> 
> I have heard of Nyquist, just forgot to apply him in this case :)
> There will be an anti aliasing filter in the front end so you wont see
> much if you put in anything close to half the sampling rate = 500Mhz.
> 
> 
> 

Anti aliasing filters do not have to be purely low pass filters set 
below the Nyquist frequency.
You can also use band pass filters to digitise a frequency above Nyquist 
or even HIGHER than the sampling frequency.

You will not get the original signal, but you will get an undersampled 
signal that still can be used in certain applications such as digital 
receivers sampling off IF chains.

The important part of the filter design is to have very good rejection 
of signals outside the designed centre frequency so no signals present 
at the usual "baseband" are present.

Obviously the ADC must be capable of functioning at the desired input 
frequency.

It works, and is quite commmon.

Ray

On Mon, 20 Jul 2009 13:48:51 -0700, "Joel Koltner"
<zapwireDASHgroups@yahoo.com> wrote:

>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message
>> Sure. Life is risky. Given a product with 200 different parts, two of
>> which are overstressed, there's probably more risk that one of the 198
>> other parts will be EOL'd.
>
>Have you ever been caught in the situation of one of your over-stressed parts 
>being changed by the manufacturer in such a way so as to render it unsuitable 
>for your needs?
>

Siemens used to make the CLY5 power mesfet. It was rated for about 9
volts or something but was good to 22 or so. They discontinued it and
TriQuint started making them, with a different process. The new ones
die hard at 15 volts. Luckily, the product that we used it on never
got beyond shipping a couple of prototypes.

Optek keeps changing their laser diodes, so you can't count on their
typical performance.

But in general we haven't had much trouble. EOL'd regular parts are a
bigger hassle because there are so many more "regular"-use parts in a
product. 

We do test parts to destruction to see what sorts of margins we have.
Some parts don't even survive their datasheet abs max ratings.

John

On Mon, 20 Jul 2009 13:55:27 -0700, Joerg <invalid@invalid.invalid>
wrote:

>John Larkin wrote:
>> On Mon, 20 Jul 2009 11:00:40 -0700, "BobW"
>> <nimby_GIMME_SOME_SPAM@roadrunner.com> wrote:
>> 
>>> "RFI-EMI-GUY" <Rhyolite@NETTALLY.COM> wrote in message 
>>> news:4a64ac0d$0$5646$9a6e19ea@unlimited.newshosting.com...
>>>> John Larkin wrote:
>>>>> On Mon, 20 Jul 2009 08:02:20 +1000, "David L. Jones"
>>>>> <altzone@gmail.com> wrote:
>>>>>
>>>>>> John Larkin wrote:
>>>>>>> On Sun, 19 Jul 2009 22:04:25 +1000, "David L. Jones"
>>>>>>> <altzone@gmail.com> wrote:
>>>>>>>
>>>>>>>> As promised, an expos� of an issue with the Rigol DS1052E
>>>>>>>> oscilloscope in my latest video blog:
>>>>>>>> http://www.alternatezone.com/eevblog/
>>>>>>>>
>>>>>>>> Dave.
>>>>>>> Do the scopes work?
>>>>>> Yep, they work. So Rigol are obviously getting away with it by hook or 
>>>>>> by crook.
>>>>>> If AD are deliberately under-speccing their normal chips, then it's a 
>>>>>> clever ploy by Rigol to exploit it.
>>>>>>
>>>>>> Dave.
>>>>> We overclock/overstress parts when there's a substantial payoff. One
>>>>> Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so
>>>>> we run it at 20. One microwave schottky diode is rated for 2 volts
>>>>> reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an
>>>>> FPGA can buy some timing margin. Some diodes and cmos parts leak four
>>>>> or five orders of magnitide less than the datasheet guarantees. An
>>>>> 0603 resistor can dissipate a quarter of a watt safely. The trick is
>>>>> to take calibrated risks where there's demonstrated margin and big
>>>>> paybacks, and take zero risk everywhere else.
>>>>>
>>>>> John
>>>>>
>>>> Doesn't the manufacturer sort of put themselves at risk that the chip 
>>>> vendor decides to change the process or ship marginal product ("Nobody is 
>>>> buying our 100 MHz parts anymore, so we will save a few bucks and make and 
>>>> ship 40 MHz parts (that pass only to 45 MHz)")?
>>>>
>>>> -- 
>>>> Joe Leikhim K4SAT
>>> Yep. That's what I would be extremely concerned about. If I ever decided to 
>>> run a part over its rated limits (speed wise), I would put in hooks, for 
>>> production testing, to lower its supplies to their minimum and then run 
>>> those tests at the maximum rated d.u.t. temperature.
>>>
>>> Of course, in Larkin's case, the only person that can fire him for non 
>>> performance and insubordination is his wife.
>>>
>> 
>> Hey, nowadays I report to The Brat.
>> 
>
>I was just going to say, didn't she show an interest in the biz lately 
>and even do a layout? Remember, she may one day be the one deciding 
>which nursing home you guys go to ;-)

She is doing all our PCB layouts and managing engineering [1]. And
doing all our press releases. Not bad for a 22-yo with a minior in
psychology and majors in softball and beer pong.

I asked her a couple of months ago, "Say, do you want this company?"
She thought about it for a few hundred milliseconds and said yes.

John


[1] And she does my schematic entry for me. I still draw pencil on
blue-grid D-size vellum.

John Larkin wrote:
> On Mon, 20 Jul 2009 13:55:27 -0700, Joerg <invalid@invalid.invalid>
> wrote:
> 
>> John Larkin wrote:
>>> On Mon, 20 Jul 2009 11:00:40 -0700, "BobW"
>>> <nimby_GIMME_SOME_SPAM@roadrunner.com> wrote:

[...]

>>>> Of course, in Larkin's case, the only person that can fire him for non 
>>>> performance and insubordination is his wife.
>>>>
>>> Hey, nowadays I report to The Brat.
>>>
>> I was just going to say, didn't she show an interest in the biz lately 
>> and even do a layout? Remember, she may one day be the one deciding 
>> which nursing home you guys go to ;-)
> 
> She is doing all our PCB layouts and managing engineering [1]. And
> doing all our press releases. Not bad for a 22-yo with a minior in
> psychology and majors in softball and beer pong.
> 
> I asked her a couple of months ago, "Say, do you want this company?"
> She thought about it for a few hundred milliseconds and said yes.
> 

Great. I remember a few years ago when you hinted that there wasn't much 
hope she'd jump in. For a friend of mine that turned out to be the case. 
One of their daughters would have the technical knack to run his 
business but it seems she's not very interested. Similar age.

> 
> [1] And she does my schematic entry for me. I still draw pencil on
> blue-grid D-size vellum.
> 

I do that less and less. Most of the time when a client needs a 
re-design I fire up the WP and CAD and have at it. Except when at the 
pool, like 30 minutes ago. Two Clearprint 1000HP-4 vellum pads always at 
the ready.

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

On Mon, 20 Jul 2009 14:51:59 -0700, Joerg <invalid@invalid.invalid>
wrote:

>RFI-EMI-GUY wrote:
>> Joerg wrote:
>>> Joel Koltner wrote:
>>>> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>>>> message
>>>>> Sure. Life is risky. Given a product with 200 different parts, two of
>>>>> which are overstressed, there's probably more risk that one of the 198
>>>>> other parts will be EOL'd.
>>>>
>>>> Have you ever been caught in the situation of one of your 
>>>> over-stressed parts being changed by the manufacturer in such a way 
>>>> so as to render it unsuitable for your needs?
>>>>
>>>
>>> Happened to another engineer: Bought tons of 5% capacitors for 
>>> production, went into Hilbert shifters. They always hand-picked the 1% 
>>> parts out of this lot and used the rest for jelly-bean stuffing. One 
>>> balmy summer day they found the first shipment that had a hole smack 
>>> in the middle of the Gaussian tolerance curve. Obviously someone had 
>>> detected a business opprotunity ... whoops.
>>>
>> 
>> Sure production ends on the part and then they look in the stockroom and 
>> find a dusty box of parts, where did they come from? Probably someone 
>> else hand picked parts and sent the rest back for restock!
>> 
Not to be too picky, but why would production end on a profitable 5%
parts line?
>
>They couldn't be that brazen unless they'd have gone to great lengths 
>such as re-belting them all. Because the good ones weren't all in front 
>section.

Likely selected out before packaging.

On 20 Jul., 03:11, krw <k...@att.bizzzzzzzzzzz> wrote:
> On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
>
> <altz...@gmail.com> wrote:
> >a7yvm109gf...@netzero.com wrote:
>
> <snip>
>
> >> You corrected the number of PLLs in the FPGA, how do they get the
> >> clocks' phases aligned?
>
> >Beats me.
> >Could be as simple as fixed tuned gate delay inside the FPGA, or could be
> >some more complex system that auto-calibrates perhaps.
>
> Tuning gate delays in an FPGA doesn't work.  Routing is over half the
> delay and there is no way to fix that part.  Every time you "wire" the
> part it'll have a different routing and your delays will be off.
> Indeed, the idea is to make sure you don't rely on placement or
> routing.
>
> <snip>

I think you can place and wire parts of it by hand to get around some
of it, but it would
still change with temperature, voltage, etc.

Some Xilinx fpgas have programmable delays in the IOs, 64taps each at
1/64th of a ~200MHz (afair)
reference clock.  a closed loop keeps the delay constant with temp
etc.

-Lasse

JosephKK wrote:
> On Mon, 20 Jul 2009 14:51:59 -0700, Joerg <invalid@invalid.invalid>
> wrote:
> 
>> RFI-EMI-GUY wrote:
>>> Joerg wrote:
>>>> Joel Koltner wrote:
>>>>> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>>>>> message
>>>>>> Sure. Life is risky. Given a product with 200 different parts, two of
>>>>>> which are overstressed, there's probably more risk that one of the 198
>>>>>> other parts will be EOL'd.
>>>>> Have you ever been caught in the situation of one of your 
>>>>> over-stressed parts being changed by the manufacturer in such a way 
>>>>> so as to render it unsuitable for your needs?
>>>>>
>>>> Happened to another engineer: Bought tons of 5% capacitors for 
>>>> production, went into Hilbert shifters. They always hand-picked the 1% 
>>>> parts out of this lot and used the rest for jelly-bean stuffing. One 
>>>> balmy summer day they found the first shipment that had a hole smack 
>>>> in the middle of the Gaussian tolerance curve. Obviously someone had 
>>>> detected a business opprotunity ... whoops.
>>>>
>>> Sure production ends on the part and then they look in the stockroom and 
>>> find a dusty box of parts, where did they come from? Probably someone 
>>> else hand picked parts and sent the rest back for restock!
>>>
> Not to be too picky, but why would production end on a profitable 5%
> parts line?
>> They couldn't be that brazen unless they'd have gone to great lengths 
>> such as re-belting them all. Because the good ones weren't all in front 
>> section.
> 
> Likely selected out before packaging.


He meant by a customer who then sent it back. If the manufacturer did 
that there would be no re-stocking process, they do it right off the 
conveyor belt.

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

On Tue, 21 Jul 2009 04:42:36 -0700 (PDT), "langwadt@fonz.dk"
<langwadt@fonz.dk> wrote:

>On 20 Jul., 03:11, krw <k...@att.bizzzzzzzzzzz> wrote:
>> On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
>>
>> <altz...@gmail.com> wrote:
>> >a7yvm109gf...@netzero.com wrote:
>>
>> <snip>
>>
>> >> You corrected the number of PLLs in the FPGA, how do they get the
>> >> clocks' phases aligned?
>>
>> >Beats me.
>> >Could be as simple as fixed tuned gate delay inside the FPGA, or could be
>> >some more complex system that auto-calibrates perhaps.
>>
>> Tuning gate delays in an FPGA doesn't work. �Routing is over half the
>> delay and there is no way to fix that part. �Every time you "wire" the
>> part it'll have a different routing and your delays will be off.
>> Indeed, the idea is to make sure you don't rely on placement or
>> routing.
>>
>> <snip>
>
>I think you can place and wire parts of it by hand to get around some
>of it, but it would
>still change with temperature, voltage, etc.

You might do it once.  You'll never maintain the mess.

>Some Xilinx fpgas have programmable delays in the IOs, 64taps each at
>1/64th of a ~200MHz (afair)
>reference clock.  a closed loop keeps the delay constant with temp
>etc.

Yes, there is an I/O delay, but it's certainly not that large.  There
is also delay in the DLLs on that order, but there are a lot of
restrictions on those (clocks only).

On Mon, 20 Jul 2009 14:51:59 -0700, Joerg <invalid@invalid.invalid>
wrote:

>RFI-EMI-GUY wrote:
>> Joerg wrote:
>>> Joel Koltner wrote:
>>>> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>>>> message
>>>>> Sure. Life is risky. Given a product with 200 different parts, two of
>>>>> which are overstressed, there's probably more risk that one of the 198
>>>>> other parts will be EOL'd.
>>>>
>>>> Have you ever been caught in the situation of one of your 
>>>> over-stressed parts being changed by the manufacturer in such a way 
>>>> so as to render it unsuitable for your needs?
>>>>
>>>
>>> Happened to another engineer: Bought tons of 5% capacitors for 
>>> production, went into Hilbert shifters. They always hand-picked the 1% 
>>> parts out of this lot and used the rest for jelly-bean stuffing. One 
>>> balmy summer day they found the first shipment that had a hole smack 
>>> in the middle of the Gaussian tolerance curve. Obviously someone had 
>>> detected a business opprotunity ... whoops.
>>>
>> 
>> Sure production ends on the part and then they look in the stockroom and 
>> find a dusty box of parts, where did they come from? Probably someone 
>> else hand picked parts and sent the rest back for restock!
>> 
>
>They couldn't be that brazen unless they'd have gone to great lengths 
>such as re-belting them all. Because the good ones weren't all in front 
>section.

We've had stuff put onto reels.  There are companies that do this.  I
doubt it would be worth it for capacitors, but maybe.  My bet is that
it was the manufacturer doing the binning.

krw wrote:
> On Mon, 20 Jul 2009 14:51:59 -0700, Joerg <invalid@invalid.invalid>
> wrote:
> 
>> RFI-EMI-GUY wrote:
>>> Joerg wrote:

[...]

>>>> Happened to another engineer: Bought tons of 5% capacitors for 
>>>> production, went into Hilbert shifters. They always hand-picked the 1% 
>>>> parts out of this lot and used the rest for jelly-bean stuffing. One 
>>>> balmy summer day they found the first shipment that had a hole smack 
>>>> in the middle of the Gaussian tolerance curve. Obviously someone had 
>>>> detected a business opprotunity ... whoops.
>>>>
>>> Sure production ends on the part and then they look in the stockroom and 
>>> find a dusty box of parts, where did they come from? Probably someone 
>>> else hand picked parts and sent the rest back for restock!
>>>
>> They couldn't be that brazen unless they'd have gone to great lengths 
>> such as re-belting them all. Because the good ones weren't all in front 
>> section.
> 
> We've had stuff put onto reels.  There are companies that do this.  I
> doubt it would be worth it for capacitors, but maybe.  My bet is that
> it was the manufacturer doing the binning.


Yes, I am sure it was the mfg. Profit maximization :-)

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.

On 22 Jul., 01:14, krw <k...@att.bizzzzzzzzzzz> wrote:
> On Tue, 21 Jul 2009 04:42:36 -0700 (PDT), "langw...@fonz.dk"
>
>
>
> <langw...@fonz.dk> wrote:
> >On 20 Jul., 03:11, krw <k...@att.bizzzzzzzzzzz> wrote:
> >> On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
>
> >> <altz...@gmail.com> wrote:
> >> >a7yvm109gf...@netzero.com wrote:
>
> >> <snip>
>
> >> >> You corrected the number of PLLs in the FPGA, how do they get the
> >> >> clocks' phases aligned?
>
> >> >Beats me.
> >> >Could be as simple as fixed tuned gate delay inside the FPGA, or could be
> >> >some more complex system that auto-calibrates perhaps.
>
> >> Tuning gate delays in an FPGA doesn't work.  Routing is over half the
> >> delay and there is no way to fix that part.  Every time you "wire" the
> >> part it'll have a different routing and your delays will be off.
> >> Indeed, the idea is to make sure you don't rely on placement or
> >> routing.
>
> >> <snip>
>
> >I think you can place and wire parts of it by hand to get around some
> >of it, but it would
> >still change with temperature, voltage, etc.
>
> You might do it once.  You'll never maintain the mess.
>
> >Some Xilinx fpgas have programmable delays in the IOs, 64taps each at
> >1/64th of a ~200MHz (afair)
> >reference clock.  a closed loop keeps the delay constant with temp
> >etc.
>
> Yes, there is an I/O delay, but it's certainly not that large.  There
> is also delay in the DLLs on that order, but there are a lot of
> restrictions on those (clocks only).

had to check, virtex5 has a programmable IOdelay, 64 taps of each
~78ps with the nominal 200MHz reference

-Lasse

"Joerg" <invalid@invalid.invalid> wrote in message
news:7cn0otF2847c9U1@mid.individual.net...
> Yes, I am sure it was the mfg. Profit maximization :-)

That is their right of course.
Selecting parts for a higher priced close tolerance sales line is hardly
anything new. As long as some people are prepared to pay for the extra cost
of testing, and as long as all items meet their respective specification
claims, then surely there is no problem. If some people are then unable to
get higher spec at the cheaper price, that is just their bad luck surely?

MrT.

On Tue, 21 Jul 2009 17:20:04 -0700 (PDT), "langwadt@fonz.dk"
<langwadt@fonz.dk> wrote:

>On 22 Jul., 01:14, krw <k...@att.bizzzzzzzzzzz> wrote:
>> On Tue, 21 Jul 2009 04:42:36 -0700 (PDT), "langw...@fonz.dk"
>>
>>
>>
>> <langw...@fonz.dk> wrote:
>> >On 20 Jul., 03:11, krw <k...@att.bizzzzzzzzzzz> wrote:
>> >> On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
>>
>> >> <altz...@gmail.com> wrote:
>> >> >a7yvm109gf...@netzero.com wrote:
>>
>> >> <snip>
>>
>> >> >> You corrected the number of PLLs in the FPGA, how do they get the
>> >> >> clocks' phases aligned?
>>
>> >> >Beats me.
>> >> >Could be as simple as fixed tuned gate delay inside the FPGA, or could be
>> >> >some more complex system that auto-calibrates perhaps.
>>
>> >> Tuning gate delays in an FPGA doesn't work. �Routing is over half the
>> >> delay and there is no way to fix that part. �Every time you "wire" the
>> >> part it'll have a different routing and your delays will be off.
>> >> Indeed, the idea is to make sure you don't rely on placement or
>> >> routing.
>>
>> >> <snip>
>>
>> >I think you can place and wire parts of it by hand to get around some
>> >of it, but it would
>> >still change with temperature, voltage, etc.
>>
>> You might do it once. �You'll never maintain the mess.
>>
>> >Some Xilinx fpgas have programmable delays in the IOs, 64taps each at
>> >1/64th of a ~200MHz (afair)
>> >reference clock. �a closed loop keeps the delay constant with temp
>> >etc.
>>
>> Yes, there is an I/O delay, but it's certainly not that large. �There
>> is also delay in the DLLs on that order, but there are a lot of
>> restrictions on those (clocks only).
>
>had to check, virtex5 has a programmable IOdelay, 64 taps of each
>~78ps with the nominal 200MHz reference

Is it fully programmable?  I surely don't remember that, though I
didn't use a Virtex-5.

On 22 Jul., 04:57, krw <k...@att.bizzzzzzzzzzz> wrote:
> On Tue, 21 Jul 2009 17:20:04 -0700 (PDT), "langw...@fonz.dk"
>
>
>
> <langw...@fonz.dk> wrote:
> >On 22 Jul., 01:14, krw <k...@att.bizzzzzzzzzzz> wrote:
> >> On Tue, 21 Jul 2009 04:42:36 -0700 (PDT), "langw...@fonz.dk"
>
> >> <langw...@fonz.dk> wrote:
> >> >On 20 Jul., 03:11, krw <k...@att.bizzzzzzzzzzz> wrote:
> >> >> On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
>
> >> >> <altz...@gmail.com> wrote:
> >> >> >a7yvm109gf...@netzero.com wrote:
>
> >> >> <snip>
>
> >> >> >> You corrected the number of PLLs in the FPGA, how do they get the
> >> >> >> clocks' phases aligned?
>
> >> >> >Beats me.
> >> >> >Could be as simple as fixed tuned gate delay inside the FPGA, or could be
> >> >> >some more complex system that auto-calibrates perhaps.
>
> >> >> Tuning gate delays in an FPGA doesn't work.  Routing is over half the
> >> >> delay and there is no way to fix that part.  Every time you "wire" the
> >> >> part it'll have a different routing and your delays will be off.
> >> >> Indeed, the idea is to make sure you don't rely on placement or
> >> >> routing.
>
> >> >> <snip>
>
> >> >I think you can place and wire parts of it by hand to get around some
> >> >of it, but it would
> >> >still change with temperature, voltage, etc.
>
> >> You might do it once.  You'll never maintain the mess.
>
> >> >Some Xilinx fpgas have programmable delays in the IOs, 64taps each at
> >> >1/64th of a ~200MHz (afair)
> >> >reference clock.  a closed loop keeps the delay constant with temp
> >> >etc.
>
> >> Yes, there is an I/O delay, but it's certainly not that large.  There
> >> is also delay in the DLLs on that order, but there are a lot of
> >> restrictions on those (clocks only).
>
> >had to check, virtex5 has a programmable IOdelay, 64 taps of each
> >~78ps with the nominal 200MHz reference
>
> Is it fully programmable?  I surely don't remember that, though I
> didn't use a Virtex-5.

when used as output delay it is programmable at compile time, when
used for input
it is programmable at compile time but can be changed at runtime.

haven't used it either think it is new for virtex5 and later

-Lasse

Mr.T wrote:
> "Joerg" <invalid@invalid.invalid> wrote in message
> news:7cn0otF2847c9U1@mid.individual.net...
>> Yes, I am sure it was the mfg. Profit maximization :-)
> 
> That is their right of course.
> Selecting parts for a higher priced close tolerance sales line is hardly
> anything new. As long as some people are prepared to pay for the extra cost
> of testing, and as long as all items meet their respective specification
> claims, then surely there is no problem. If some people are then unable to
> get higher spec at the cheaper price, that is just their bad luck surely?
> 

Yep, and I told them this was going to happen one fine day. So they had 
to find another brand with non-notched Gaussian.

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.